Disclosed embodiments are related to packages and methods of manufacturing the same, and more particular to wafer level chip scale packages (WLCSP) and methods of manufacturing the same.
An integrated circuit is a group of electronic circuits on a block of semiconductor material, usually silicon. Semiconductor integrated circuits are fabricated in a front-end process including operations of imaging, deposition, and etching, which are supplemented by doping and cleaning. Once the front-end process has been completed, a wafer is prepared for testing and packaging.
Many different packaging technologies have been developed, including wafer-level packaging technologies. The wafer-level packaging technologies are completed in the wafer form and individual units are finished after the wafer is sawed. In a wafer-level packaging technology, molding material is compressed against a thinned wafer after bumps are disposed on contact pads of the wafer. During compression molding, compression force generates stresses on the wafer, which likely damages thinner portions of the wafer.
Furthermore, conventional molding material cannot transmit light, including infrared light, and if alignment marks are covered by mold, the alignment marks cannot be utilized during a laser marking operation. Moreover, since conventional molding material blocks light, visual inspection is obstructed. Conventional molding material also has poor heat dissipation capability. In addition, when a wafer is diced through, chipping may occur, which may cause an adverse effect to critical areas of the wafer. The chipping may create shadows during inspection, and if so, an additional inspection operation is required to determine whether the shadows are actual defects.